Abstract
As of late progressed computerized process requests more refined parameters, for example, throughput, power and territory. It is extremely hard to keep up high throughput while keeping up ideal power utilization and cell territory. In the vast majority of the advanced frameworks multipliers are choosing their execution as far as above parameters. In the present work rapid Vedic multipliers are composed with pipeline innovation. As the MAC speed is chosen by Vedic Multiplier, in the present paper Multiplier and Accumulator (MAC) is outlined with two-way pipeline innovation to meet high throughput. Vedic Multipliers are utilized as a part of outlining MAC unit as they are quick multipliers and further improving the information speed. This article explores on the performance analysis MAC using Nikhilam sutra multiplier which is the fast multiplier among the other vedic multiplication algorithms. The MAC unit was designed using Nikhilam sutra multiplier and the adder was implemented using various design methods. The performance comparison of each MAC design implemented with different adders was described below. The MAC was implemented in both ASIC and FPGA design flows.
Keywords: Multiply – Accumulate Unit (MAC), Nikhilam sutra multiplier, Parallel Prefix Adder, Vedic Multiplier .
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