Abstract
The purpose of this work is to design, implement and experimentally verify an Arithmetic Logic Unit (ALU) using Low Power Barrel Shifter. Barrel shifter is most widely used in ALU to perform fast shifting operations. This work evaluates the performance of ALU with optimized design of barrel shifter in 130nm CMOS process technology. Dynamic logic with no precharge pulse propagation problem and recent circuit techniques for low leakage power are employed to optimize shifter unit of ALU for low power consumption. At first, the circuits were simulated with shifter modules without applying the SVL and GDI circuit. And secondly, SVL circuit was incorporated in the shifter modules for simulation. Measurement results validate the proposed concept and verify that SVL technique based shifter results in lowering the power consumed in ALU.
Keywords: Dynamic Logic Families, Low power, ALU, Barrel Shifter, Multiplexer, Self controllable Voltage Level circuit
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