Abstract
In this paper, we portray a vitality proficient Vedic multiplier structure utilizing Energy Efficient Adiabatic Logic (EEAL). The power utilization of the proposed multiplier is essentially low on the grounds that the vitality exchanged to the heap capacitance is generally recuperated. The proposed 8x8 CMOS and adiabatic multiplier structure have been planned in a TSMC 0. 18 μm CMOS process innovation and checked by Cadence Design Suite. Both simulation and estimation results confirm the usefulness of such rationale, making it reasonable for implementing energy-mindful and execution - effective very-substantial scaling proportion (VLSI) hardware. The conventional and pipeline Adiabatic Vedic multiplier were discussed in this article.
Keywords: Multiply – Adiabatic logic, Pipeline, multiplier, Vedic Multiplication, CMOS, single phase, low-power.
References
1) M. Chanda, S> Banerjee, D. saha and S. Jain, “Novel Transistor Level Realization of Ultra Low Power High-Speed Adiabatic Vedic
Multiplier,” IEEE Conference, ISBN: 978-1-4673-5090-7 pp. 801–806, April 2013.
2) P. P. Kundu, O. Bandyopadhyay, A. Sinha, "An efficient architecture of RNS based Wallace Tree multiplier for DSP applications," Proceedings 51st Midwest Symposium on Circuits and Systems, Knoxville, TN, pp. 221, 10-13 Aug. 2008.
3) Z. Gang, H. Michalik and L. Hinsenkamp, “Complexity Analysis and Efficient Implementations of Bit Parallel Finite Field Multipliers Based on Karatsuba-Ofman Algorithm on FPGAs” IEEE Trans. on VLSI system, vol. 18, no. 7, pp. 1057-1066.
4) J. Chen, C. H. Chang, “High-Level Synthesis Algorithm for the Design of Reconfigurable Constant Multiplier,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 12, pp. 1844-1856, 2009.
5) M.E Paramasivam and R.S Sabeenian, “An efficient bit reduction binary multiplication algorithm using Vedic methods,” IEEE 2nd International Advance Computing Conference, Patiala, India, pp. 25, 19-20 Feb. 2010.